New Xilinx ISE 6.1i Software Demonstrates Major Leap in Capability & Performance Leadership With 250 New Features

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Additionally, ISE version 6.1i gives designers an easy way to create high-speed memory interfaces operating at over 200Mhz through new automatic local clock routing, as well as new support for native RedHat Linux, unmatched high-speed design capabilities, and enhanced ease-of-use features for floorplanning and pin management. The combination of these new features dramatically reduces customer's overall design cycle times and design costs.

"Last quarter, Xilinx saw a sequential 33% increase in design seats sold raising our cumulative number of installed software seats to 175,000 users," said Rich Sevcik, senior vice president of FPGA Products at Xilinx. "Xilinx's focus on programmable logic design methodology has resulted in the industry's most cost effective, robust software suite delivering the greatest advances in PLD software performance, capability, and ease of use in the last five years."

Unrivaled High-Speed Design

ISE version 6.1i delivers unique high-speed design capabilities such as new timing constraints. For example, the new clock jitter constraint, the ability to specify the true data valid window, and the addition of individual package pin flight time reporting provides more accurate place and route results for source synchronous designs. Designers using Virtex-II and Virtex-II Pro FPGAs have access to 96 local high-speed clocks that can be routed to keep clock skew within the range required for 200Mhz SDR, DDR, and QDR RAM interfaces. ISE 6.1i includes an enhanced mapping feature for ProActive Timing Closure that performs logic placement so that mapping decisions can be made based on physical location -- resulting in an additional 13% faster clock speeds and 23% better utilization compared to ISE 5.2i. Also, for push-button flows, ISE 6.1i delivers a 16% performance improvement over ISE 5.2i.

The World's Easiest to Use PLD Design Software

ISE 6.1i sets the industry standard for ease-of-use with new and enhanced features that solve traditional design bottlenecks to speed design and verification. For example, Project Navigator (advanced design-flow based project manager) enables synthesis tools from Mentor Graphics to graphically view post synthesis technology schematics to quickly refine timing constraints. Project Navigator also enables users of synthesis tools from Synplicity and Xilinx to mix VHDL and Verilog HDL source in the same project, allowing designers to use legacy IP and HDL design resources to achieve the best possible results. Users can also link to and launch the Xilinx Embedded Design Kit (EDK) XPS project manager, as well as use the new Automatic Web Update feature which monitors software updates, notifies users, and if selected, downloads the files necessary to keep a user's ISE configuration current.

PACE (Pinout and Area Constraints Editor) which offers easy graphical pin layout and management has been dramatically enhanced and now includes new CPLD support. PACE now supports the capability to enter pin definitions before an HDL source design exists, eliminating the need to complete designs before going to PCB layout. PACE also supports comma-separated value (CSV) bi- directional file transfer, resulting in better integration with PCB layout design tools.

Easier debug during timing simulation can now be achieved with the ability to write out multiple HDL and SDF files to match the original hierarchy of a design.

Xilinx Silicon & Software: The Ideal ASIC Replacement

Xilinx's proven software and silicon leadership has accelerated the industry-wide transition from ASICs to FPGA technology. Increasingly, customers are looking for more flexible, low cost solutions in the face of uncertain market conditions, skyrocketing NRE and mask costs, and shortened time-to-market windows and product lifecycles. The new software suite, coupled with Virtex-II Pro and Spartan-3 FPGAs offering breakthrough price points, device densities, and performance, offer designers an ideal ASIC replacement solution. Designers can now take "push button" advantage of the world's first 90nm FPGAs -- the Spartan-3 family from Xilinx with up to 5 million system gates -- to dramatically reduce overall design time and costs without the verification headaches traditionally associated with ASICs.

Additionally, the Xilinx solution provides designers with a superior solution to so-called "Structured ASICs" which are plagued by long development times and high upfront costs and lack the flexibility, inexpensive software tools, and robust IP library available today with Xilinx FPGAs. The inherent reprogrammability of Xilinx FPGAs enables designers to get products to market more quickly by accelerating design debug and reducing overall support costs.

Price, evaluation version, platform and availability

ISE 6.1i supports all leading-edge Xilinx product families including the company's Virtex-II Pro Series FPGAs, Spartan-3 Series FPGAs, and CoolRunner- II CPLDs. All versions of ISE software packages support Windows 2000 and Windows XP and ISE Foundation, ISE Alliance, and ISE BaseX also support native Linux RedHat versions 7.3 and 8.0. ISE Foundation and ISE Alliance also support Solaris. All in-maintenance Xilinx customers began receiving ISE upgrades in early September. Pricing for ISE starts at $695. The 6.1i version of ISE WebPACK will be available for free download in mid-September of 2003. ISE is also available in a free, time-limited, full-featured evaluation version at http://www.xilinx.com/. For more details on ISE please visit http://www.xilinx.com/faster.

About Xilinx

Xilinx, Inc. is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at http://www.xilinx.com/.

CONTACT: Jennifer Wright of Xilinx, Inc., +1-408-879-7727, or
Jennifer.wright@xilinx.com

Web site: http://www.xilinx.com/